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Low-Power Integrated Circuit Design Optimization Approach

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dc.contributor.author Y. A. Durrani
dc.date.accessioned 2023-03-14T03:31:24Z
dc.date.available 2023-03-14T03:31:24Z
dc.date.issued 2016-01-04
dc.identifier.citation Durrani, Y. A. (2016). Low-power integrated circuit design optimization approach. Technical Journal, UET, Taxila, 21, 32-42. en_US
dc.identifier.issn 2313-7770
dc.identifier.uri http://142.54.178.187:9060/xmlui/handle/123456789/18794
dc.description.abstract Abstract— In this tutorial survey, the paper presented a general review of the state-of-the-art techniques in optimizing the power dissipation on digital electronic systems. The source of power dissipation is focused on complementary metal-oxide-semiconductor (CMOS) circuits. This basic information cannot be implemented directly to optimize power dissipation due to the low abstraction level, but will be helpful to solve the power related problem. The major power factors are considered for the hardware and the software with the most rustful approaches of all levels of the design flow. The paper review is organized in three different types of digital system design: interpret conceptually, design flow, and management. en_US
dc.language.iso en en_US
dc.publisher Taxila: University of Engineering and Technology, Taxila en_US
dc.subject Low-power en_US
dc.subject Power Optimization en_US
dc.subject Power Estimation en_US
dc.title Low-Power Integrated Circuit Design Optimization Approach en_US
dc.type Article en_US


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