Fabrication and Structural Characterization of Co-implanted Ultra Shallow Junctions for Integration inPiezoresistive Silicon Sensors Compatible withCMOS Processing

Abstract

Fabrication and structural characterization of Indium and Carbon imp lanted n -type Silicon layers forming ultra-shallow junction for integration in piezoresistive sensors compatible with CMOS processing is studied in detail. The co-imp lantation technology together with mediu m range annealing temperature regimes seem to play an important role at atomistic level and provide a process control to engineer the strain and maintain the quality of surface/layer/active device region for further manufacturing process cycle. This is likely to impact the yield and reliability for the fabrication of these devices for diverse applications.