Optimization Techniques for Throughput Enhancement in FPGA Specific Designs

Abstract

The prime goal of design and synthesis of Digital Signal Processing (DSP) algorithms and architectures is to meet the throughput requirements of an application in a hardware-economic fashion. Economics of hardware implementation includes an improvement in resource utilization, and power consumption, in the context of widely accepted application performance metrics, such as design throughput, spectral purity, and algorithmic precision. DSP tasks are usually computationally intensive and involve complex operations in real or pseudo-real-time. Choice of implementation hardware platform thus depends upon application requirements such as minimum data rate and signal fidelity keeping within the resource utilization and power consumption budgets. Realization of such cost effective hardware systems requires use of several complexity reduction methods and optimization techniques. Modern Field Programmable Gate Arrays (FPGAs) include complex slice fabric, intricate routing architectures, large input lookup tables, and specialized hardware blocks. Apart from the configurable logic blocks and routing structure present in classical FPGAs, modern FPGAs have built-in computational blocks for specialized functions. However, optimal system performance, in terms of clock speed, device utilization ratio, and power consumption, can only be achieved with meticulous and careful use of these advanced and specialized hardware resources. Standardized design optimizations used in Application Specific Integrated Circuits (ASICs) cannot be directly employed for algorithms to be implemented on FPGAs because of the fixed layout and routing structure of FPGAs. Harnessing the power and flexibility of FPGAs to their full potential to achieve requisite performance and efficiency gains for these cutting-edge applications, necessitates development of customized algorithmic and architectural optimizations. This work concerns two major domains of DSP hardware implementations, firstly, to gain performance enhancement by optimal mapping of digital designs onto the FPGA hardware and secondly, to architect algorithmic transformations for modifying the application architecture to the one more conformant to FPGA implementation. Which in turn, involves the reduction of computational complexity by reducing the number of multipliers and adders as well as achieving the higher data rates through pipelining and efficient encoding. vAdvanced optimizations and customizations for core DSP applications, such as Finite Impulse Response (FIR) filters, Infinite Impulse Response (IIR) filters, complex multipliers, various architectural transformations of multi-input adders, Coordinate Rotation Digital Computer (CORDIC), and multi-rate interpolation and decimation filter implementations have been proposed during the course of this work. Furthermore, this thesis proposes novel design methodologies for generating architectures for optimal mapping on these modern FPGAs containing specialized computational blocks and hardware functional units. The new methods keep in perspective the architectural peculiarities of the target FPGAs, and additionally, apply transformations to achieve higher throughput. The resulting architectures have shown substantial improvement over state of the art designs reported in literature.