Designing and Simulation of Silicon Carbide based devices for Power Applications

Abstract

This research focuses on the designing and simulation of normally-on and normally- off 4H-SiC VJFET. In the present study, concepts of controlling and improving the device characteristics have been discussed by employing geometrical parameters, such as drift layer thickness and channel width along with doping concentration. A two dimensional numerical device simulator, Sentaurus TCAD, is used to design, model and optimize the structures of SiC VJFET. The extraction of parameters through finite element simulation is also a prime focus of this research. Based on the review of SiC JFET, different structures are designed to address some important parameters that are not readily accessible when using experimental methods. The relationship between electric field, electron mobility and electron velocity is also discussed through finite element simulation. The effect of channel concentration on breakdown and forward characteristics is discussed and devices are shown to behave normally-off in the selected range of channel concentrations from 1 x 1015 cm-3 to 9 x 1015 cm-3. Herein, we theoretically report the presence of bipolar mode at high gate voltage in 4H-SiC VJFET for the first time. To the best of our knowledge, these observations are not yet discussed experimentally. The theoretical evidence showing the presence of bipolar mode at high gate voltage hence reduces the current gain and specific on-resistance which ultimately effects the device performance. These investigations will definetly help improve the functionality of experimentally desigened devices afterwards. Temperature-dependent high voltage breakdown characteristics of normally-off 4H-SiC VJFET are also simulated, utilizing the wider drift layer thickness of 120 μm. In order to investigate the temperature-dependent electric field and impact ionization distribution, finite element simulation is performed. The distribution of electric field revealed the punch-through behavior which provides high breakdown voltage capability at narrow channel opening in case of zero gate bias or wider channel opening under limited negative gate bias. Furthermore, the device exhibits a negative temperature coefficient for breakdown voltage. Breakdown voltages are obtained with the dependence of channel widths demonstrating that negative gate voltage is required to obtain the maximum breakdown voltage. Furthermore, the effects of drift layer thickness with the dependence of drift doping on the breakdown voltage and specific on-resistance are discussed. Detailed analyses of design parameters are performed with the set of parameters used in the process calibration. The obtained results are compared with the experimental and theoretical reported data, demonstrating that the proposed structures show a good validation between simulation and experiments.