Delay- Adaptation in FPGA based Asynchronous Micropipeline Architectures

Abstract

Digital asynchronous designs are gradually attaining attractions of designers due to their potential for high-speed, low-power and no clock skews, however, their implementation is not an easy task. Asynchronous systems exist in full custom domain like ASIC, however, rare attempts were made for their implementation on reconfigurable test bench e.g. FPGAs platforms. This is mainly due to the difficulty of producing coordination between processing of data and the respective control signals. Processing of data being considerably slow compared with the speed of control signals, especially if the later are generated independent of processing. Attempts were made to synchronize them by inserting predefined delay pads in the control path which not only slow down the systems but run those on fixed delays, an approach close to the synchronous processing. Further, the approach was not much successful in improving the efficiency of the systems because accurate modeling of the precise needed delay, itself being a cumbersome job, is impractical at pre-synthesis stage as the routing tools may generate a different ratio between control and data paths thus altering the needed delays. On the other hand, in ASIC, the designers can implement any needed digital as well as analog circuits, e.g., the need was generation of a control signal at completion of execution. In ASIC, the completion detection circuit can be implemented by sensing the amount of current flowing in a circuit because of transitions, which when cease the current drops to almost zero. Although current sensing has its own implications, neither such circuits are available nor could be built in FPGAs, and the designers have to use only the provided resources. Moreover, conventional vii FPGAs and their programming tools are made for synchronous systems and provide a little facilitation towards asynchronous designs implementation. This thesis presents, a logic-based execution completion detection circuit that detects the completion of execution by processing blocks to store only the valid results. This circuit eliminates the need of estimation of delays and placing delay pads in control path. It also permits the designers the use of auto place-and-route, mapping and auto-optimizing tools for the implementation of asynchronous designs on conventional FPGAs. The completion detection circuitry not only caters to the logic and interconnect delays dynamically but also generates the control signals as sequence controller for smooth functionality of the processor catering to the synchronization problem. It also acts as inter-stage latch in a micropipeline based asynchronous systems. Based on the proposed concepts, a delay-adaptive micropipeline model is presented that can contain any sequential or combinational circuit. The micropipeline based on the proposed concepts was implemented as RISC processor. It was observed that the RISC processor exhibited smooth functionality and over 10% improvement on power-delay product in comparison to its synchronous counterpart. The same concepts also demonstrated their ability to make technology-independent asynchronous systems. This thesis is an attempt to provide solutions to hindrances towards the design and implementation of asynchronous systems on reconfigurable platforms that will open up new doors of research in this field.