Study and Analysis of Space Radiation Effects on VLSI Microelectronics Devices''

Abstract

This research thesis presents the assessment/determination of level of hazard/threat to emerging microelectronics devices in Low Earth Orbit (LEO) space radiation environment with different orbital parameters to predict the performance of onboard memories and/or random logic devices fabricated in 65 nm technology node. In this context, the various parameters for space radiation environment have been analyzed to characterize the ionizing radiation environment effects on proposed VLSI devices. The space radiation environment has been modeled in the form of particles trapped in Van-Allen Earth Radiation Belts (ERBs), Energetic Solar Particles Event (ESPE) and Galactic Cosmic Rays (GCRs) whereas its potential effects on Device- Under-Test (DUT) has been predicted in terms of Total Ionizing Dose (TID), Single-Event Effects (SEE) and Displacement Damage Dose (DDD). The required mitigation techniques including necessary shielding requirements to avoid undesirable effects of radiation environment at device level has been determined with assumed typical Aluminum shield thickness of 100 mils or 2.54 mm. In order to evaluate space radiation environment and analyze energetic particles effects on six transistors (6T) Static Random Access Memory (SRAM) bit-cell, Outil de Modélisation de l‟Environnement Radiatif Externe (OMERE) toolkit developed by Tests & Radiations (TRAD) company/organization located at Toulouse France was utilized. Therefore, this thesis focuses on the radiation response of 6T SRAM bit-cell circuits operating in radiation environment existing at LEO. The performance of bulk CMOS technology based devices was evaluated by characterizing its susceptibility to Single Event Upsets (SEUs). Further, the impact of technology scaling on SEU rates, Linear Energy Transfer (LET) threshold and area of cross-section per bit/device due to ionizing radiation environment at an altitude up to 1000 km was simulated. Due to irradiation of gate and drain regions of off-state NMOS transistor in SRAM bit cell with LET spectrum of particles transmitted through shielding, the magnitude and pulse duration of generated transient current translated to voltage pulses were analyzed. The sensitive strike locations for 65 nm SRAM bitcell were presented in SEU map whereas Cumulative Distribution Function (CDF) for upset probability regarding SEU occurrence was presented as a function of Vdmin i.e. minimum differential voltage between the internal complementary storage nodes of SRAM represented by Q Q (Q-bar). Finally, the SEU sensitive parameters required to predict SEU rate of on-board target device i.e. 65nm SRAM was calculated with typical Aluminum spot shielding using fully physical mechanism simulation. Moreover, contribution of Multiple Cell Upsets (MCUs) towards total SEU rate for 65nm SRAM bitcell was determined with Multi Scale Single Event Phenomenon Prediction Platform (MUSCA SEP3) toolkit The effect of TID on MOS devices in LEO environment to cause electrostatic potential variations and drain leakage current “Id” was determined with Genius device simulator module of Visual TCAD. Finally, effect of Displacement Damage Dose (DDD) was estimated for 1 MeV electron and 10 MeV protons fluence with the help of OMERE-TRAD toolkit. In order to characterize the robustness of scaled CMOS devices, state of the art simulation tools such as Klayout, GDS2MESH, Visual TCAD/Genius, GSEAT/Visual Particle, runSEU and MUSCA SEP3 were utilized whereas LEO radiation environment assessment as well as single event upset rate prediction was accomplished with the help of OMERE-TRAD software.